Past REU Participants & Project Pages

2006 REU Porjects
2006 REU Projects
2006 Participant: Roger H. Kienast
Project Title: An Improved Design for Sscaling Mmagneto-Resistive Random Access Memory Structures

Faculty Advisor:Dr. Mircea Stan
MRAM (Magnetic Random Access Memory) is a high-speed, high-density, nonvolatile memory technology with an estimated unlimited endurance. By using Magnetic Tunnel Junctions for data storage and magnetic fields to write data bits, MRAM has fast read/write times and uses low power. Itís long-term data retention and rapid on/off processes (negligible boot time) may replace DRAM, SRAM, or Flash memories in most mobile handheld electronic systems. MRAM may also replace backup batteries because it protects memory contents in the event of an unexpected loss of power. However, MRAM still has a way to go before replacing current memories into a single, universal solution. There are some problems with magnetic field disturbances when scaling the array, and in the future there may be a limit to how small the array can be constructed due to large silicon transistor technology. Also, the manufacturing cost of MRAM needs to decrease, and the technology must be accepted into society before MRAM will take off. I will be demonstrating the different architectures of MRAM, different read/write processes that can be used, a potential solution to some scaling issues, and show current developments for the technology.
MRAM still has a few kinks to work out. As MRAM arrays are scaled down, more power will be needed to read and write. The resulting magnetic fields will more easily interfere with other cells and create noise in the structure. Another problem with scaling this technology is that in the future, transistors will be much larger than the cells, and we will not be able to make the pitch any smaller. I proposed a design that not only reduces the number of transistors needed to read cells, but also lowers the magnetic field interferences from unintended currents looping through other cells in the array by 33%. The design also relocates the fewer transistors to the peripheral circuitry, allowing an increase in density by more than two times. Unfortunately, my proposal requires three times as many Digit Lines and the angling aspect may be more complicated to manufacture. Also with more DLs, more decoding logic will be needed
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